1. Field of the Invention
The present invention relates to a programmable logic device, and more particularly a programmable logic device capable of relieving a defective product and thereby improving a yield, and a control program, a circuit forming method and a circuit design system related thereto, and an apparatus having the programmable logic device mounted thereon.
2. Description of the Related Art
Presently, circuit design using a programmable logic device (hereafter abbreviated as PLD) is widely carried out. In a programmable logic device chip, wiring of an internal circuit group can be designed externally, and logic operation can be programmed even after manufacturing. The PLD includes a complex programmable logic device (CPLD) and a field programmable gate array (FPGA).
The PLD has a storage for storing circuit information specifying a design of the wiring connections of the internal circuit group, and the logic operation can be programmed arbitrarily by modifying the circuit information stored in the storage. The wiring connection design of the internal circuit group can be performed by executing a program, which is called allocation and wiring software, executed in information processing equipment such as a personal computer (PC) being externally connected to the PLD via a parallel cable, etc. In many cases, PLD manufacturers provide the allocation and wiring software or a program (write software) for storing the circuit information into the storage, to developers free of charge. Therefore, once purchasing the PLD, the developers can perform the circuit design at low cost.
In order to improve a product yield of the PLD in the prior art, redundant elements are incorporated in the device, in addition to the functions which are inherently required. When a defect occurs in the manufacturing process, by using such a redundant element as a replacement, it is possible to relieve the product, which would originally be treated as a defective product without the redundant elements. Such a technique has been used in a memory device. For example, according to the official gazette of the Japanese Unexamined Patent Publication No. 2002-319296, there is disclosed a semiconductor device having redundantly prepared memory blocks, which includes a redundant address decoder to avoid an access to the memory block including a defective element. Also, in the official gazette of the Japanese Unexamined Patent Publication No. H11-211794, there is described a method of replacing with a standby memory cell by disconnecting a metal fuse on the occurrence of a defect. Further, as a prior art related to relief of a defective product, the official gazette of the Japanese Unexamined Patent Publication No. H5-267607, discloses a method of relieving a defect in one base block. According to this disclosure, a set of the input values, which causes an actual output value different from the accurate value to be originally output, is stored in a memory in advance, and the output is reversed when the set of the input values stored in memory is input. Then error is corrected and the base block is relieved.